1. Field of the Invention
The present invention relates to a method of driving a liquid crystal display device and a driver circuit for driving a liquid crystal display device, and more particularly to a method of driving a liquid crystal display device and a driver circuit for driving a liquid crystal display device for an ultra-high fine and multi-gray scale display with reducing an electro-magnetic interference.
2. Description of the Related Art
A liquid crystal display has a liquid crystal panel including an array of pixels, each of which includes a pixel electrode and a switching transistor. The switching transistor comprises a thin film transistor. A voltage having a corresponding voltage level to a gray scale is applied through the thin film transistor to the pixel electrode.
It would be important for the liquid crystal display to realize an ultra-high fine display and an increased high speed driving performance of the liquid crystal panel with an increased number of the pixels and an increased area of a display screen.
FIG. 1 is a block diagram illustrative of a first conventional driver circuit for driving a liquid crystal display. The liquid crystal display includes a display panel 50 and a driver circuit having the following circuit configuration.
The display panel 50 has an array of pixels, each of which includes a pixel electrode and a thin film transistor. The thin film transistor has a gate electrode connected to a gate signal line 501, a source electrode connected to a source signal line 502 and a drain electrode connected to the pixel electrode. The display panel 50 also has a plurality of gate signal lines 501 extending in a row direction and a plurality of source signal lines 502 extending in a column direction.
The driver circuit includes a row alignment of plural source drivers 30 and a column alignment of plural gate drivers 40. The number of the source drivers 30 is “N”, whilst the number of the gate drivers 40 is “M”. Each of the source drivers 30 is connected to a plurality of the source signal lines 502 for driving the source signal lines 502. Each of the gate drivers 40 is connected to a plurality of the gate signal lines 501 for driving the gate signal lines 501.
The driver circuit farther includes a graphic controller 11, a transmitter 12 and an interface board 20. On the interface board 20, a receiver unit 201, a display control unit 202 and a power supply circuit 203 are provided. The graphic controller 11 outputs control signals and image data which are then transmitted through the transmitter 12 to the receiver unit 201. The control signals include timing control signals. The timing control signals may for example, be a clock signal, a horizontal synchronous signal, and a vertical synchronous signal.
The receiver unit 201 receives the timing control signals and the image data from the graphic controller 11. The timing control signals and the image data are then supplied to the display control unit 202. The display control unit 202 generates a gate driver clock signal, a frame start signal, a source driver clock signal and a start signal based on the timing control signals as well as generates image signals based on the image data. The gate driver clock signal and the frame start signal are supplied to the gate drivers 40. The source driver clock signal and the start signal are supplied to the source drivers 30.
The power supply circuit 203 generates powers supplied to the source drivers 30, another power supplied to a common electrode of the display panel 50 and still another power supplied to the gate driver.
The image data and the timing control signals are supplied in parallel-transmission from the graphic controller 11 to the transmitter 12. The transmitter 12 performs a parallel-to-serial conversion of the image data and the timing control signals, so that the image data and the timing control signals are supplied in serial-transmission from the transmitter 12 to the receiver unit 201. The serial data including the image data and the timing control signals may be transmitted in any available transmission system such as a low voltage differential signaling (LVDS), a transmission minimized differential signaling (TMDS), a gigabit video interface (GVIF) and a low voltage differential signaling display interface (LDI).
The receiver unit 201 performs a serial-to-parallel conversion of the image data and the timing control signals, so that the image data and the timing control signals are supplied in parallel-transmission from the receiver unit 201 to the display control unit 202.
Each of the source drivers 30 accepts an input of the image data or incorporates the image data based on the start signal and in synchronization with the source driver clock signal, and then each source driver 30 converts the image data into corresponding voltage levels to the image data for applying the source signal lines 502 with respective gray-scale voltage signals having the corresponding voltage levels, so that the voltage signals are transmitted through the source signal lines 502 and the thin film transistors to the pixel electrodes.
Each of the gate drivers 40 drives the gate signal lines 501 sequentially one-by-one based on the frame start signal and in synchronization with the gate driver clock signal. The thin film transistors connected to the gate signal line 501 on the selection are placed to allow the gray-scale voltage signals to be transmitted from the source signal lines 502 through the thin film transistors to the pixel electrodes.
There were proposed following plural conventional methods of display controls in timing of supply of the image data and the source driver clock signals to the source drivers 30 and also in timing of accepting the inputs of the image data into the source drivers 30.
FIG. 2 is a fragmentary block diagram illustrative of a first conventional circuit configuration including a timing controller and source drivers, wherein the circuit configuration is included in the circuit configuration of FIG. 1. FIG. 3 is a view illustrative of contents of image data to be supplied in synchronization with a clock signal from the timing controller to the source drivers 30 in FIG. 2.
The display control unit 202 includes a timing controller 202A shown in FIG. 2. The timing controller 202A has a clock port “clock signal”, from which the source driver clock signal is supplied to the source drivers 30. The timing controller 202A also has a first data port “A-port”, from which odd-number image data for the pixels of odd numbers is supplied to the source drivers 30. The timing controller 202A also has a second data port “B-port”, from which even-number image data for the pixels of even numbers is supplied to the source drivers 30. The odd-number image data may be referred to as “A-port image data” and the even-number image data may be referred to as “B-port image data”.
As shown in FIG. 3, the image data includes red-color data of 8-bits, green-color data of 8-bits, and blue-color data of 8-bits. For the 8-bits data, eight signal lines are provided. The image data is isolated into the odd-number image data and the even-number image data. Namely, each of the red-color green-color, and blue-color data is isolated into the odd-number image data or the even-number image data. The odd-number image data (or A-port image data) comprises plural sets of the red-color, green-color, and blue-color data for the odd-number pixels. The even-number image data (or B-port image data) comprises plural sets of the red-color, green-color, and blue-color data for the even-number pixels.
The timing controller 202A generates a clock signal “clock signal” having the same cyclic frequency as a data rate of the above image data. The image data and the clock signal are supplied from the timing controller 202-A to the source drivers 30, so that each of the source drivers 30 incorporates the image data at a timing of a rising edge timing of the clock signal for generating corresponding gray-scale voltages to the image data, whereby each of the source drivers 30 applies the gray-scale voltages onto the source signal lines 502. The above A-port data, the B-port data, and the clock signal are common signals to all of the source drivers 30.
FIG. 4 is a fragmentary block diagram illustrative of a second conventional circuit configuration including a timing controller and source drivers, wherein the circuit configuration is included in the circuit configuration of FIG. 1. FIG. 5 is a view illustrative of contents of image data to be supplied in synchronization with a clock signal from the timing controller to the source drivers in FIG. 4.
The display control unit 202 includes a timing controller 202B shown in FIG. 4. The timing controller 202B has a clock port “clock signal”, from which the source driver clock signal is supplied to all of the source drivers 3B1, 3B2, 3B3, 3B4, - - - . The timing controller 202B also has a first data port “A-port”, from which A-port image data is supplied to the source drivers 3B1, 3B3, - - - . The timing controller 202B also has a second data port “B-port”, from which B-port image data is supplied to the source drivers 3B1, 3B3, - - - . The timing controller 202B also has a third data port “C-port”, from which C-port image data is supplied to the source drivers 3B2, 3B4, - - - . The timing controller 202B also has a fourth data port “D-port”, from which D-port image data is supplied to the source drivers 3B2, 3B4, - - - .
The timing controller 202B generates a clock signal “clock signal” having the same cyclic frequency as a data rate of the above image data. The timing controller 202B also generates the A-port data, the B-port data, the C-port data, and the D-port data, wherein the image data comprises plural sets of four-data units. First two-data units are divided into the even numbers and the odd numbers as the A-port data and the B-port data. Second two-data units are divided into the even numbers and the odd numbers as the C-port data and the D-port data.
The image data and the clock signal are supplied from the timing controller 202B to the source drivers 3B1, 3B2, 3B3, 3B4, - - - , so that each of the source drivers 3B1, 3B2, 3B3, 3B4, - - - incorporates the image data at a timing of a rising edge timing of the clock signal for generating corresponding gray-scale voltages to the image data, whereby each of the source drivers 3B1, 3B2, 3B3, 3B4, - - - applies the gray-scale voltages onto the source signal lines 502. The clock signal is a common signal to all of the source drivers 3B1, 3B2, 3B3, 3B4, - - - .
FIG. 6 is a fragmentary block diagram illustrative of a third conventional circuit configuration including a timing controller and source drivers, wherein the circuit configuration is included in the circuit configuration of FIG. 1. FIG. 7 is a view illustrative of contents of image data to be supplied in synchronization with a clock signal from the timing controller to the source drivers in FIG. 6.
The display control unit 202 includes a timing controller 202C shown in FIG. 6. The timing controller 202C has a first clock port “clock signal 1”, from which a first source driver clock signal is supplied to odd-number source drivers 3B1, 3B3, - - - . The timing controller 202C has a second clock port “clock signal 2”, from which a second source driver clock signal is supplied to even-number source drivers 3B2, 3B4, - - - . The second source driver clock signal is delayed by a half cycle from the first source driver clock signal, so that the second source driver clock signal is opposite in phase to the first source driver clock signal.
The timing controller 202C also has a first data port “A-port”, from which A-port image data is supplied to the source drivers 3B1, 3B3, - - - . The timing controller 202C also has a second data port “B-port”, from which B-port image data is supplied to the source drivers 3B1, 3B3, - - - . The timing controller 202C also has a third data port “C-port”, from which C-port image data is supplied to the source drivers 3B2, 3B4, - - - . The timing controller 202C also has a fourth data port “D-port”, from which D-port image data is supplied to the source drivers 3B2, 3B4, - - - .
As described above, the image data are isolated into four-system image data, for example, the A-port image data, the B-port image data, the C-port image data and the D-port image data. The A-port image data and the B-port image data are supplied to odd number source drivers 3B1, 3B3, - - - on odd number stages. The C-port image data and the D-port image data are supplied to even number source drivers 3B2, 3B4, - - - on even number stages. The C-port image data and the D-port image data are different in phase by a half data cycle from the A-port image data and the B-port image data.
As shown in FIG. 7, the four system image data include first odd-and-even two system image data for the adjacent two source drivers 3B1 and 3B2 and second odd-and-even two system image data for the following adjacent two source drivers 3B3 and 3B4 on the follower stages to the source drivers 3B1 and 3B2.
The timing controller 202C generates the first and second clock signals “clock signal 1” and “clock signal 2” having the same cyclic frequency as a data rate of the above image data but different in phase by a half cycle from each other, wherein the first clock signal “clock signal 1” is supplied to the odd number source drivers 3B1, 3B3, - - - , whilst the second clock signal “clock signal 2” is supplied to the even number source drivers 3B2, 3B4, - - - . The timing controller 202C also generates the A-port data, the B-port data, the C-port data, and the D-port data, wherein the image data comprises plural sets of four-data units. First two-data units are divided into the even numbers and the odd numbers as the A-port data and the B-port data. Second two-data units are divided into the even numbers and the odd numbers as the C-port data and the D-port data, which are delayed by a half cycle from the A-port data and the B-port data.
The image data and the clock signal are supplied from the timing controller 202C to the source drivers 3B1, 3B2, 3B3, 3B4, - - - . Each of the odd-number source drivers 3B1, 3B3, - - - incorporates the image data at a timing of a rising edge timing of the first clock signal “clock signal 1” for generating corresponding gray-scale voltages to the image data, whereby each of the odd-number source drivers 3B1, 3B3, - - - applies the gray-scale voltages onto the source signal lines 502. Each of the even-number source drivers 3B2, 3B4, - - - incorporates the image data at a half-cycle-delayed timing of the rising edge timing of the second clock signal “clock signal 2” for generating corresponding gray-scale voltages to the image data, whereby each of the even-number source drivers 3B2, 3B4, - - - applies the gray-scale voltages onto the source signal lines 502.
FIG. 8 is a fragmentary block diagram illustrative of a fourth conventional circuit configuration including a timing controller and source drivers, wherein the circuit configuration is included in the circuit configuration of FIG. 1. FIG. 9 is a view illustrative of contents of image data to be supplied in synchronization with a clock signal from the timing controller to the source drivers in FIG. 8. This fourth conventional circuit configuration is disclosed in Japanese laid-open patent publication No. 10-340070. A frequency of the clock signal can be reduced without increasing the width of the data bus for transmitting the image data.
The display control unit 202 includes a timing controller 202D shown in FIG. 8. The timing controller 202D has a first clock port “clock signal 1”, from which a first source driver clock signal is supplied to odd-number source drivers 3B1, 3B3, - - - . The timing controller 202D has a second clock port “clock signal 2”, from which a second source driver clock signal is supplied to even-number source drivers 3B2, 3B4, - - - . The second source driver clock signal is delayed by a half cycle from the first source driver clock signal, so that the second source driver clock signal is opposite in phase to the first source driver clock signal.
The timing controller 202D also has a first data port “A-port”, from which A-port image data is supplied to all of the source drivers 3B1, 3B2, 3B3, 3B4, - - - . The timing controller 202D also has a second data port “B-port”, from which B-port image data is supplied to all of the source drivers 3B1, 3B2, 3B3, 3B4, - - - .
As described above, the image data is isolated into two-data systems, for example, odd number data and even number data. The timing controller 202D generates the first and second clock signals “clock signal 1” and “clock signal 2” having the same cyclic frequency as a data rate of the above image data but different in phase by a half cycle from each other, wherein the first clock signal “clock signal 1” is supplied to the odd-number source drivers 3B1, 3B3, - - - , whilst the second clock signal “clock signal 2” is supplied to the even-number source drivers 3B2, 3B4, - - - . The first and second clock signals “clock signal 1” and “clock signal 2” have a cyclic frequency corresponding to a half of the data rate of the image data. The timing controller 202D also generates the A-port data and the B-port data.
The image data and the clock signal are supplied from the timing controller 202D to the source drivers 3B1, 3B2, 3B3, 3B4, - - - . Each of the odd-number source drivers 3B1, 3B3, - - - incorporates the image data at a timing of a rising edge timing of the first clock signal “clock signal 1” for generating corresponding gray-scale voltages to the image data, whereby each of the odd-number source drivers 3B1, 3B3, - - - applies the gray-scale voltages onto the source signal lines 502. Each of the even-number source drivers 3B2, 3B4, - - - incorporates the image data at a half-cycle-delayed timing of the rising edge timing of the second clock signal “clock signal 2” for generating corresponding gray-scale voltages to the image data, whereby each of the even-number source drivers 3B2, 3B4, - - - applies the gray-scale voltages onto the source signal lines 502.
In accordance with the fourth conventional method, the image data for the adjacent two source drivers 3B1 and 3B2 are isolated into two systems, for example, even number data and odd number data, and also the image data for the follower two source drivers 3B3 and 3B4 following to the adjacent two source drivers 3B1 and 3B2 are also isolated into two systems, for example, even number data and odd number data. The odd and even numbers data are subjected to a time-division multiplexing to form the A-port data and the B-port data.
In accordance with the above conventional methods, the data rate is defined by the width of each box indicating the content of the image data, for example, R0, G0, and B0 shown in FIGS. 3, 5, 7 and 9. The cyclic frequency of the clock signal is defined by the waveform shown in FIGS. 3, 5, 7 and 9.
The first, second and third conventional methods have the following disadvantages. As shown in FIGS. 3, 5 and 7, the cyclic frequency of the clock signal is equal to the data rate of the image data. This means that the frequency of transition in voltage level of the clock signal is higher by two times than the data rate of the image data. The improvement in the high definition and the increase in the area of the display panel would cause the increase of the image data for each source line, whereby the frequency of the clock signal is thus increased. The increase in the frequency of the clock signal would raise a problem with the electromagnetic interference. Namely, the characteristic in the electromagnetic interference of the liquid crystal display device is deteriorated.
In order to avoid the deterioration in the characteristic in the electromagnetic interference of the liquid crystal display device, it is effective to reduce the frequency of the clock signal. For the reasons described above, it is, however, difficult for the first, second and third conventional methods to respond to the requirement for increase of the image data for each source line without increase in the frequency of the clock signal. Namely, it would be difficult to satisfy both requirements for the increase of the image data and for avoiding the problem with the electromagnetic interference.
On the other hand, the above described fourth conventional method utilizes the clock signal having the cyclic frequency which is a half of the data rate as shown in FIG. 9. This fourth conventional method is suitable for reducing the frequency of the clock signal and for avoiding the problem with the electromagnetic interference.
The fourth conventional method is to reduce the frequency of the clock signal without increase in the width or the number of the data bus, for which reason it is difficult to realize a desirable high speed data processing or data transmission. This means it difficult to realize a desirable improvement in high definition and a desirable increase in size of the display screen of the liquid crystal display panel. The two system image data make it more difficult to realize the desirable improvement in high definition and the desirable increase in size of the display screen of the liquid crystal display panel.
The but lines for transferring the image data are provided for the primary three colors, for example, red, green and blue separately. This increases the total number of the necessary bus lines for transferring the image data, and also increases the times of changing the voltage levels or the bit values of the bus lines. This emphasizes the problem with the electromagnetic interference.
The electromagnetic interference provides the undesirable influence to operations of peripheral electric, electronic or electron devices. The provision of any counter-measure tool against the electromagnetic interference increases the cost. Further, it is difficult to distinguish an electromagnetic noise radiated from the bus line from other electromagnetic noises.
The above conventional methods are also engaged with a further problem with the cross-talk noise which may cause data error.
In the above circumstances, the developments of a novel method of driving a liquid crystal display device and of a novel driver circuit for driving a liquid crystal display device free from the above problems is desirable.